CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today multimedia requires at least an 8MB and preferably even a 16 MB memory, which increases the relative cost of the memory system within a computer. In the near future, it is likely that 32 MB and 64 MB computers will become commonplace, which suggests a potential demand for 256 Mb DRAMs (Dynamic Random Access Memory) and beyond. Despite the huge array size and lithographic difficulties that ensue, it is more important than ever to increase the chip yield. Process engineers are constantly attempting to reduce and ultimately, eliminate or at the very least, mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs, and more specifically redundancy replacement.
Conventional redundancy configurations typically revolve about a Fixed Size Redundancy Replacement (FSRR) architecture, wherein elements are grouped in units containing a fixed number of elements, which are used to replace defective elements within the memory device.
Various configurations within the FSRR architecture have been successfully implemented over the years. A typical FSRR configuration, which is commonly used for low density DRAMs is shown in FIG. 1a. Therein are depicted a fixed plurality of spares used for replacing defective elements within the memory and which are appended to each sub-array comprising the memory. Each redundancy unit (RU) is comprised of a plurality of redundancy elements (REs), (e.g., two RE per RU are illustrated therein), and which are used to repair existing faults (labeled X) within the corresponding sub-array. This scheme, labeled intra-block replacement, increases the redundancy area overhead as the number of sub-blocks increases for high density memories, since each sub-block requires its own, one or preferably two RUs. Thus, the efficiency of the RUs is rather poor in view of its inflexibility which reduces the chip yield substantially when faults are clustered in a given sub-array. The above mentioned concept is embodied in a configuration described in the article by T. Kirihata et al., entitled "A 14 ns 4 Mb DRAM with 300 mW Active Power", published in the IEEE Journal of Solid State Circuits, Vol. 27, pp. 1222-1228, September 1992.
Another FSRR redundancy replacement arrangement, known as a flexible redundancy replacement configuration is shown in FIG. 1b, wherein a memory is depicted having a single array of RUs to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU can repair faults (labeled X) located in any sub-array within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely, a redundancy array, having a fixed number of RUs may advantageously be used to service any number of sub-arrays forming the memory. This translates into a substantial saving of real estate over the previous scheme, although it requires a substantial amount of additional control circuitry to properly service all the sub-arrays forming the memory.
There is yet another FSSR architecture, referred to block FSRR, and shown in FIG. 1c, wherein any number of faults (including all the faults) in a sub-array are replaced with a block redundancy. The size of the prior art block FSRR coincides with that of the sub-array, the sub-array being defined as a section of memory contained between sense amplifier strips. Since in this scheme, a defective block is replaced by a good block, it ensues that all defective REs contained within a block are simultaneously replaced by good REs. Although this replacement methodology introduces a new dimension in the repairability of defects, it also brings along a significant amount of added design space to accommodate the various configurations that make this architecture so desirable. Moreover, there is a significant drawback in that block redundancy cannot be used if the redundancy block itself has a fault, even if only one. Since, by definition, a block is large, the probability of finding at least one defect in the redundancy block is high. Although the subdivision of arrays depicted in FIG. lc is known in the art, no provisions exist to provide appropriate corrections when defects affect the block redundancy array.
More details regarding the above configurations and the various trade-offs may be found in an article by T. Kirihata et al., "A Fault-Tolerant Design for 256 Mb DRAMs", published in the Digest of Technical Papers of the 1995 Symposium on VLSI Circuits, pp. 107-108; in an article by T. Sugibayashi et al., "A 30 ns 256 Mb DRAM with Multi-divided Array Structure", published in the IEEE Journal of Solid State Circuits, vol. 28, pp. 1092-1098, November 1993; and in an article by H. L. Kalter et al., "A 50 ns 16 Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, vol. 25, pp. 1118-1128, October 1990.
In summary, a Fixed Size Redundancy Replacement (FSRR) arrangement consists of a fixed number of replacement units, each with the same number of REs to correct defects in the memory device. The flexibility of allocating a predetermined number of fixed-sized redundancy units allows the units and the control circuitry to be shared among the several memory sub-arrays, thereby significantly increasing the effective usage of the redundancy. This configuration has demonstrated its value by providing good repairability, specially of bit lines, (either single bits or multiple bits); wordlines, (either single words or multiple words), and the like, all falling under the category of "hard faults".
Yet, FSRR suffers from a distinct disadvantage in that it still requires a significant number of RUs (and corresponding control circuitry) to overcome another class of faults, labeled "retention faults", in which a bit, stored in the capacitor that forms a DRAM cell, fades away over time in a weak cell, thereby producing a fault. This problem is of utmost importance, particularly, since retention faults far exceed the number of hard faults.
Referring back to the hard faults within a memory, defects of this type tend to cluster, thereby ideally requiring a customized unit containing an equivalent number of redundancy elements. Hard faults are typically not too numerous, but their size can in itself be quite large, thereby necessitating multiple REs and/or large size REs to repair such faults. By way of example, if a sub-array contains four clustered defects, a 4-elements redundancy unit would be required to replace them. However, if five clustered defects were present, and only units containing four REs were available, the replacement of defects could potentially fail altogether in the intra-block replacement configuration (because not enough units would be available within the sub-array to service this number of faults). Similarly, a flexible replacement configuration also falls short since, in practice, only units of the "wrong size" are available to perform the repair, although flexible redundancy schemes are more likely to provide successful replacement than the intra-block replacement architecture.
Retention faults, on the other hand, occur randomly throughout the memory, and their number is typically high; yet, there is a distinct advantage in that they can be repaired with a single RE. In the intra-block replacement configuration, retention faults can only be serviced by RUs containing a fixed plurality of REs. Clearly, if RUs containing only one RE were designed with the intention of detecting randomly occurring retention faults, then such a configuration would be ideal for retention faults; yet they fall short for servicing hard faults (e.g, four units having one RE each would be needed to service a cluster of four hard faults). Retention faults are also difficult to repair even with a flexible redundancy replacement architecture because of the large number of such faults, which frequently may overwhelm the repair circuitry available in the memory device.
In view of the foregoing, the goal of an ideal redundancy configuration is to repair hard faults, retention faults, and block faults, whether randomly distributed throughout the memory or clustered therein, without introducing an onerous burden caused by a complex redundancy area overhead. Typically, this overhead is divided into: a redundancy element overhead and redundancy control circuitry overhead, both of which should be minimized to achieve good repairability and maintain optimum performance of the memory.
Related redundancy configurations, including some of the categories listed above, are described in the following references:
U.S. Pat. No. 5,491,664 to Phelan, issued Feb. 13, 1996, describes the implementation of a flexible redundancy memory block elements in a divided array architecture scheme. This configuration has both, the memory and the redundant memory blocks, coupled to a read bus to allow the redundancy memory in one memory sub-array to be shared by a second sub-array.
U.S. Pat. No. 5,475,648 to Fujiwara, issued Dec. 12, 1995, in which a memory having a redundancy configuration is described such that when an appropriate address signal agrees with the address of a defective cell, a spare cell provided by the redundant configuration is activated to replace the failing one.
U.S. Pat. No. 5,461,587 to Seung-Cheol Oh, issued Oct. 24, 1995, in which a row redundancy circuit is used in conjunction with two other spare row decoders, wherein by a judicious use of fuse boxes, signal generated by a row redundancy control circuit make it possible to replace failing rows with spare ones.
U.S. Pat. No. 5,459,690 to Rieger at al., issued Oct. 17, 1995, describes a memory with a redundant arrangement that, in the presence of normal wordlines servicing defective memory cells, enables faulty memory cells to be replaced with redundant cells.
U.S. Pat. No. 5,430,679 to Hiltebeitel et al., issued Jul. 4, 1995, describes a fuse download system for programming decoders for redundancy purposes. The fuse sets can be dynamically assigned to the redundant decoders, allowing a multi-dimensional assignment of faulty rows/column within the memory.
U.S. Pat. No. 5,295,101 to Stephens, Jr. et al., issued Mar. 15, 1994, describes a two level redundancy arrangement for replacing faulty sub-arrays with appropriate redundancy elements.
Whereas the prior art and previous discussions have been described mainly in terms of DRAMs, practitioners of the art will fully appreciate that the above configurations and/or architectures are equally applicable to other types of memories, such as SRAMs, ROMs, EPROMs, EEPROMs, Flash RAMs, CAMs, and the like.